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FTCircuitBench

Error correction proposal

Suite of 160+ algorithm instances compiled into Clifford+T and Pauli-based computation forms to score fault-tolerant resource costs for surface-code and qLDPC architectures.

Measures
Fault-tolerant resource costs of compiled algorithm circuits: T-count, gate counts, depth, rotation-synthesis fidelity, space-time volume, and structural metrics
Introduced by
Harkness et al. (Pacific Northwest National Laboratory & academic collaborators) (2026)

FTCircuitBench is a proposed benchmark suite for the fault-tolerant compilation stack: whole algorithm circuits are compiled end-to-end and scored on logical resource costs, with no device ever run. Released in January 2026 by a PNNL-led team with university collaborators, it targets the gap left by NISQ-era circuit suites: once circuits must be expressed in Clifford+T or Pauli-based computation and laid out on an error-corrected architecture, the metrics that matter change entirely. It is catalogued under error correction because its subject is QEC-era compilation and architecture, though its unit of evaluation is a full algorithm circuit, in the tradition of software suites like Benchpress and MQT Bench.

How it works

The suite provides 160+ benchmark instances (ripple-carry adders, QFT, Hamiltonian simulation, phase estimation, HHL, and QSVT circuits) plus a pipeline that compiles each into Clifford+T and Pauli-based computation (PBC) forms targeting surface-code and qLDPC architectures. Compiled outputs are scored on fault-tolerant resource costs (T-count, gate counts, depth, rotation-synthesis fidelity, and space-time volume) alongside structural metrics such as Pauli weight and modularity that indicate how a workload maps onto a given architecture.

Strengths and limitations

It is among the first suites built for the fault-tolerant era rather than retrofitting NISQ workloads, and covering both Clifford+T and PBC targets lets architecture studies compare paradigms on equal workloads (Harkness et al. 2026). All metrics come from compilation and numerical analysis, never from executing circuits on quantum hardware, and results reflect toolchain versions at test time.

Its standing is precarious: a January 2026 proposal with no journal version or arXiv revision, whose official GitHub repository (footnoted in the paper) went dark sometime before July 2026: it now returns 404, and only third-party mirrors preserve the MIT-licensed commit history. It was presented at Unitary Foundation’s Quantum Wednesday seminar in February 2026, but independent adoption is not yet established. Not to be confused with QASMBench, the same group’s NISQ-era circuit suite, or FTPrimitiveBench, an overlapping team’s suite for logical primitives under biased noise.

Key papers

Reference implementations

  • FTPrimitiveBench : Stim-based suite that scores logical error rates of surface-code Clifford primitives (memory, lattice surgery, transversal Hadamard, and the S gate) under hardware-motivated biased noise.
  • Benchpress : IBM's open-source suite of 1,000+ timed tests comparing how fast quantum SDKs construct, manipulate, and transpile circuits, plus the quality of the compiled output.
  • MQT Bench : Library of 70,000+ benchmark circuits, each served at four abstraction levels, so quantum compilers, simulators, and verifiers can be compared on common workloads.