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ACES

Characterization

Scalable characterization protocol that estimates the Pauli error rates of every gate and measurement on a processor simultaneously from a small set of shallow Clifford circuits

Measures
Pauli error rates of every gate and measurement across a whole processor, estimated simultaneously from averaged circuit eigenvalues
Introduced by
Flammia (AWS Center for Quantum Computing / Caltech) (2021)
Also known as
Averaged circuit eigenvalue sampling, Average circuit eigenvalue sampling

ACES (averaged circuit eigenvalue sampling) is a characterization protocol introduced by Steven Flammia at the AWS Center for Quantum Computing that estimates the Pauli error rates of every gate and measurement on a processor at once. Where randomized benchmarking and its interleaved and simultaneous variants each isolate one gate or qubit subset at a time, ACES strictly generalizes them into whole-device noise metrology: a detailed noise model rather than a headline score, sitting in the QCVV toolbox alongside gate set tomography and cycle benchmarking.

How it works

The device runs a small set of shallow random Clifford circuits. Under Pauli noise, each circuit damps Pauli observables by an averaged circuit eigenvalue that is a product of the eigenvalues of the gates it contains. Estimating enough circuit eigenvalues gives a linear system (in the logarithms) that inverts to per-gate and per-measurement Pauli error rates across the whole processor. The original paper demonstrated the scheme numerically on 100 qubits using fewer than 20 circuits; QuantumACES.jl automates circuit design and fitting for large devices.

Strengths and limitations

ACES recovers a full Pauli noise model of a processor from remarkably few circuits, strictly generalizing component-level randomized benchmarks. It reconstructs stochastic Pauli noise: implementations typically tailor noise with Pauli twirling (the IBM-device demonstration characterized Pauli channels without twirling), so coherent errors enter only through their averaged Pauli-channel effect. Two bibliographic traps: the primary paper appeared as a six-page extended abstract in Proc. TQC 2022 (the ACES paper published in the journal Quantum is the 2026 fermionic extension), and follow-up work spells the name both “averaged” and “average”.

Notable results

ACES has run on IBM’s Algiers and Osaka processors (Pelaez et al., 2024) and on coupled superconducting qubits, with estimates verified against interleaved randomized benchmarking (Palomaki et al., 2025). An extension to syndrome-extraction circuits appeared in PRX Quantum 6, 010334 (2025) alongside the maintained QuantumACES.jl package, and a fermionic generalization in Quantum 10, 2053 (2026). For per-cycle rather than per-gate error profiles, see cycle error reconstruction.

Key papers

Reference implementations

  • Cycle error reconstruction : Keysight True-Q diagnostic that reconstructs the probabilities of the individual Pauli errors afflicting a cycle of parallel gates, with multiplicative precision
  • Cycle benchmarking : Pauli-twirled decay protocol that measures the process fidelity of an entire cycle of parallel gates at once, scaling to whole devices where interleaved benchmarking cannot.
  • Gate set tomography : Calibration-free tomography that reconstructs every gate, state preparation, and measurement in a gate set simultaneously and self-consistently, yielding predictive error models rather than a single score.